The invention relates to a vertical SOI device usable for power applications, such as an IGBT (insulated gate bipolar transistor) or power diodes, wherein the SOI device comprises a vertical drift zone and an emitter configuration, which may be implemented by a fabrication methodology according to the SOI (silicon on insulator) technology using isolation trenches.
Due the utilization of positive and negative charge carriers the IGBT provides significant advantages with respect to a reduced on resistance relative to unipolar DMOS transistors in particular at higher voltage ranges, e.g., at 600 Volts. Different from the unipolar vertical NDMOS transistor additional positive charge carriers are typically injected into the device from a specifically design backside. In order to be able to control the concentrations of charge carriers it is, however, necessary to adjust the electrically activated and effective doping profile as a function of the depth of this so-called backside emitter in a very precise manner.
For discrete devices the fabrication of the highly doped backside emitter is performed at the end of the wafer processing. In this way the degree of an undue interaction with the front side processes and in particular with high temperature processes potentially resulting in an undesired diffusion of the backside dopants and hence a change of the doping profile and thus a change in electrical characteristics of the backside emitter may significantly be reduced or avoided.
An integration of such a vertical IGBT into an SOI semiconductor wafer has the consequence that the backside emitter is positioned within the wafer volume. Therefore the backside emitter may no longer be processed at the final stage of the process, since for instance a doping process by ion implantation in the deeper volume of the wafer where the backside emitter is to be formed is associated with severe disadvantages and may thus typically not be applicable. For this reason the backside emitter is frequently incorporated at the initial stage of the process, i.e., prior to the bonding of the device wafer and the carrier wafer to form an SOI substrate. In this case further high temperature steps for forming the devices may have to be taken into consideration, since they may affect the configuration of the backside emitter. Therefore laterally arranged IGBT are frequently integrated into SOI substrates. In the lateral configuration the emitter is no longer positioned in the volume but is located at the front side and may thus be formed by usual doping processes. The lateral configuration of the transistor is disadvantageous in that an increased area is required on the SOI wafer for a transistor having the same resistance compared to a corresponding vertical configuration.
Vertical IGBTs typically have a dopant distribution that is homogenously distributed across the entire backside. However, devices are known in the art, in which the backside emitter is doped in a local varying manner. For example, U.S. Pat. No. 6,259,123 discloses a structure having a backside structure formed from highly n-doped island regions which are positioned within a highly p-doped continuous region.
B. Jayant Baliga, “Power Semiconductor Devices”, PWS Publishing Company Boston, 1995, page 180 discloses a diode structure in which also the cathode in the form of a backside doping is alternately provided with n+-type and p+-type conductivity.
These structures are advantageous in that the efficiency of the emitter is more conveniently adjustable by photolithographic techniques, i.e., substantially by the area ratios between the n+ and p+ regions, as is the case by controlling the doping profile. Hence, respective structures are significantly more sensitive to high temperature steps of the actual semiconductor manufacturing process. It is a disadvantage that these emitter structures are not integrated in the SOI substrate, since the n+ and p+ regions in the volume of the SOI substrate are not simultaneously contacted.